1. Technical Field
The present invention relates to ferroelectric memory devices, and in particular, to readout technology for ferroelectric memory devices.
2. Related Art
For reading a ferroelectric memory device (FeRAM: Ferroelectric Random Access Memory), a method employing a latch-type sense amplifier circuit may be used. In this case, the voltage applied to the plate line is voltage-divided between the ferroelectric capacitor capacitance (Cs) and the bit line capacitance (Cbl). As a result, an adequate potential is not applied to ferroelectric capacitors due to the bit line capacitance (Cbl). Furthermore, because differences in bit line voltages are amplified by a sense amplifier and readout, the more the bit line capacitance (Cbl) increases, the smaller the bit line voltage becomes, so that the sense margin decreases.
Accordingly, readout circuits which can fix bit lines at virtual ground potentials are being examined (e.g., bit line GND sense system). Ferroelectric memory devices according to the aforementioned system are described in, for example, Japanese Laid-open Patent Application JP-A-2002-133857 (Patent Document 1), Published International Application WO 2004/093088 (Patent Document 2) and Japanese Laid-open Patent Application JP-A-2005-293818 (Patent Document 3).
According to the bit line GND sense system described above, a capacitance Ctank for storing a negative charge is used for fixing the pMOS (MOS: Metal Oxide Semiconductor) that controls the supply of charge to the bit line and the bit line at the ground (GND) potential. By supplying the negative charge stored in the capacitance Ctank to the bit line through the pMOS, the potential on the bit line can be virtually fixed at the ground potential (see Patent Document 1).
In this case, readout is conducted through detecting a potential change at the other end of the capacitance Ctank, which is the amount of charge supplied from the capacitance Ctank. However, as the potential is a negative potential, it needs to be converted to a positive potential, and thereafter inputted and amplified by a sense amplifier.
For example, according to the circuit (shown in FIG. 1) described in Patent Document 2, a negative potential on the node VNEG is inputted in the sense amplifier SA through the capacitor Ctrans. Also, according to the circuit (shown in FIG. 3) described in Patent Document 3, a negative potential at the node MINS is outputted through the level shift circuit 22.
However, if the conversion efficiency in converting a negative potential to a positive potential is low, the readout margin would lower, and therefore further improvement in the potential conversion efficiency is desired. Also, simplification and area-reduction of the circuit structure are desired.